Figure 13.26 Iric Setting Timing And Scl Control (2) - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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When WAIT = 1, and FS = 0 or FSX = 0 (I
SCL
8
SDA
8
IRIC
User processing
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL
8
SDA
8
IRIC
User processing
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.

Figure 13.26 IRIC Setting Timing and SCL Control (2)

Rev. 1.00, 05/04, page 332 of 544
2
C bus format, wait inserted)
9
A
Clear IRIC
Clear IRIC
9
A
Clear IRIC
1
2
1
2
Write to ICDR (transmit)
or read from ICDR (receive)
3
3
1
1
Clear IRIC

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