Table 10.3 Clock Input To Tcnt And Count Condition (2) - Renesas H8S/2111B Hardware Manual

Table 10.3 Clock Input to TCNT and Count Condition (2)

Channel CKS2 CKS1
TMR_Y 0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
TMR_X 0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Notes: 1. If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock
input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
2. The program development tool (emulator) does not support TCRXY. Selection of the
internal clock is only available when CKSX = 0 and CKSY = 0.
Rev. 1.00, 05/04, page 194 of 544
TCR TCRXY*
CKS0 CKSX
0 —
1 —
0 —
1 —
0 —
0 —
1 —
0 —
1 —
0 —
1 —
0 —
1 —
0 0
1 0
0 0
1 0
0 0
0 1
1 1
0 1
1 1
0 1
1 —
0 —
1 —
2
CKSY Description
0 Disables clock input
Increments at φ/4
0
Increments at φ/256
0
Increments at φ/2048
0
0 Disables clock input
1 Disables clock input
Increments at φ/4096
1
Increments at φ/8192
1
Increments at φ/16384
1
1 Increments at overflow signal from
1
TCNT_X*
— Increments at rising edge of external
clock
— Increments at falling edge of external
clock
— Increments at both rising and falling
edges of external clock
— Disables clock input
Increments at φ
—
Increments at φ/2
—
Increments at φ/4
—
— Disables clock input
— Disables clock input
Increments at φ/2048
—
Increments at φ/4096
—
Increments at φ/8192
—
— Increments at compare-match A from
1
TCNT_Y*
— Increments at rising edge of external
clock
— Increments at falling edge of external
clock
— Increments at both rising and falling
edges of external clock