Figure 18.10 Erase/Erase-Verify Flowchart - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
Table of Contents

Advertisement

Increment
address
NG
Notes:
1. Prewriting (writing 0 to all data in erased block) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 22.5, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units.
4. Set only a single bit in EBR1 and EBR2. Do not set more than one bit.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.

Figure 18.10 Erase/Erase-Verify Flowchart

START
* 1
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
Set EBR1 and EBR2
Enable WDT
Set ESU bit in FLMCR2
Wait (y) µs
Set E bit in FLMCR1
Wait (z) ms
Clear E bit in FLMCR1
Wait (α) µs
Clear ESU bit in FLMCR2
Wait (β) µs
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
Set block start address
as verify address
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
NG
Verify data
= all "1"?
OK
NG
Last address
of block?
OK
Clear EV bit in FLMCR1
Wait (η) µs
* 2
* 5
All erase blocks erased?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
End of erasing
* 2
* 4
* 2
Start of erasing
* 2
End of erasing
* 2
* 2
* 2
* 2
* 3
Clear EV bit in FLMCR1
Wait (η) µs
n≥ (N) ?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
Erase failure
Rev. 1.00, 05/04, page 449 of 544
n ← n + 1
* 2
* 2
NG

Advertisement

Table of Contents
loading

This manual is also suitable for:

Hd64f2111b

Table of Contents