Renesas H8S/2111B Hardware Manual page 412

Bit Bit Name
3 IBFIE3
2 IBFIE2
1 IBFIE1
0 ERRIE
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined
6 CLKRUN Undefined
5 SERIRQ Undefined
4 LRESET Undefined
3 LPCPD Undefined
2 PME Undefined
1 LSMI Undefined
0 LSCI Undefined
Rev. 1.00, 05/04, page 378 of 544
R/W
Initial
Value Slave Host
0 R/W —
0 R/W —
0 R/W —
0 R/W —
R/W
R —
R —
R —
R —
R —
R —
R —
R —
Description
IDR3 and TWR Receive Completion Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive completed
interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive completed interrupt
requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive completed
interrupt requests enabled
IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed interrupt
requests disabled
1: Input data register (IDR2) receive completed interrupt
requests enabled
IDR1 Receive Completion Interrupt Enable
Enables or disables IBFI1 interrupt to the slave
processor (this LSI).
0: Input data register (IDR1) receive completed interrupt
requests disabled
1: Input data register (IDR1) receive completed interrupt
requests enabled
Error Interrupt Enable
Enables or disables ERRI interrupt to the slave
processor (this LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
LFRAME Pin Monitor
CLKRUN Pin Monitor
SERIRQ Pin Monitor
LRESET Pin Monitor
LPCPD Pin Monitor
PME Pin Monitor
LSMI Pin Monitor
LSCI Pin Monitor