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Renesas Manuals
Computer Hardware
H8S/2111B
Hardware manual
Figure 15.5 Power-Down State Termination Timing - Renesas H8S/2111B Hardware Manual
Bit single-chip microcomputer h8s family / h8s/2100 series
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Figure 15.5 shows the timing of the LPCPD and LRESET signals.
LCLK
LPCPD
LAD3–LAD0
LFRAME
LRESET
Rev. 1.00, 05/04, page 404 of 544
At least 30 µs
Figure 15.5 Power-Down State Termination Timing
At least 100 µs
At least 60 µs
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