Usage Notes; Kbioe Setting And Kclk Falling Edge Detection; Figure 14.14 Kbioe Setting And Kclk Falling Edge Detection Timing - Renesas H8S/2111B Hardware Manual

14.5

Usage Notes

14.5.1

KBIOE Setting and KCLK Falling Edge Detection

When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 14.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
KCLK (pin)
Internal KCLK
(KCLKI)
KBIOE
Falling edge
signal
KBFSEL
KBE
KBF

Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing

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Rev. 1.00, 05/04, page 365 of 544