Renesas H8S/2111B Hardware Manual page 276

Bit single-chip microcomputer h8s family / h8s/2100 series
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Bit
Bit Name
3
PER
2
TEND
1
MPB
0
MPBT
Note:
*
Only 0 can be written, to clear the flag.
Rev. 1.00, 05/04, page 242 of 544
Initial
Value
R/W
0
R/(W)*
1
R
0
R
0
R/W
Description
Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
Transmit End
[Setting conditions]
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive frame.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit frame.

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