External Trigger Input Timing; Figure 16.4 External Trigger Input Timing; Table 16.3 A/D Conversion Time (Single Mode) - Renesas H8S/2111B Hardware Manual

Table 16.3 A/D Conversion Time (Single Mode)

Item
A/D conversion start delay
time
Input sampling time
A/D conversion time
Note: * Values in the table indicate the number of states.
16.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.4 shows the
timing.
ADTRG
Internal trigger
signal
ADST
Rev. 1.00, 05/04, page 422 of 544
Symbol
t
D
t
SPL
t
CONV
φ

Figure 16.4 External Trigger Input Timing

CKS = 0
Min. Typ. Max.
10 — 17
— 63 —
259 — 266
A/D conversion
CKS = 1
Min. Typ. Max.
6 — 9
— 31 —
131 — 134