Instruction Set; Table 2.1 Instruction Classification - Renesas H8S/2111B Hardware Manual

2.6

Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function
Data transfer
Arithmetic
operations
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer EEPMOV
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. B is the general name for conditional branch instructions.
CC
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.
Instructions
MOV
1 1
POP* , PUSH*
5 5
LDM* , STM*
3
MOVFPE* , MOVTPE*
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
4
TAS*
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
2
B * , JMP, BSR, JSR, RTS
CC
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
3
Size
B/W/L
W/L
L
B
B/W/L
B
B/W/L
L
B/W
W/L
B
B/W/L
B/W/L
B
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Rev. 1.00, 05/04, page 29 of 544
Types
5
19
4
8
14
5
9
1
Total: 65