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12.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared.
Bit
Bit Name
7
TDRE
6
RDRF
5
ORER
4
FER
Initial
Value
R/W
1
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and
TDR is ready for data write
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
Overrun Error
[Setting condition]
•
When the next data is received while RDRF = 1
[Clearing condition]
•
When 0 is written to ORER after reading ORER = 1
Framing Error
[Setting condition]
•
When the stop bit is 0
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
Rev. 1.00, 05/04, page 241 of 544
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