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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register
(SYSCR).
Product Classification
Flash memory version
Section 17 RAM
RAM Capacitance
H8S/2111B-B 2 Kbytes
H8S/2111B-C 3 Kbytes
RAM Address
H'E880 to H'EFFF,
H'FF00 to H'FF7F
H'E480 to H'EFFF,
H'FF00 to H'FF7F
Rev. 1.00, 05/04, page 429 of 544
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