Figure 13.31 Stop Condition Issuance Timing - Renesas H8S/2111B Hardware Manual

2
9. Note on when I C bus interface stop condition instruction is issued
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
SCL
SDA
IRIC
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 342 of 544
Secures a high period
9th clock
VIH
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination

Figure 13.31 Stop Condition Issuance Timing

Stop condition generation
[2] Stop condition instruction issuance