Renesas H8S/2111B Hardware Manual page 10

2.8 Processing States............................................................................................................... 46
2.9 Usage Notes ...................................................................................................................... 48
2.9.1 Note on TAS Instruction Usage........................................................................... 48
2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48
2.9.3 Note on Bit Manipulation Instructions ................................................................ 48
2.9.4 EEPMOV Instruction........................................................................................... 49
Section 3 MCU Operating Modes ..................................................................... 51
3.1 MCU Operating Mode Selection ...................................................................................... 51
3.2 Register Descriptions........................................................................................................ 52
3.2.1 Mode Control Register (MDCR) ......................................................................... 52
3.2.2 System Control Register (SYSCR)...................................................................... 53
3.2.3 Serial Timer Control Register (STCR) ................................................................ 55
3.3 Operating Mode Descriptions ........................................................................................... 56
3.3.1 Mode 2................................................................................................................. 56
3.3.2 Mode 3................................................................................................................. 56
3.4 Address Map ..................................................................................................................... 57
Section 4 Exception Handling ........................................................................... 59
4.1 Exception Handling Types and Priority............................................................................ 59
4.2 Exception Sources and Exception Vector Table ............................................................... 60
4.3 Reset ................................................................................................................................. 61
4.3.1 Reset Exception Handling ................................................................................... 61
4.3.2 Interrupts after Reset............................................................................................ 62
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................ 62
4.4 Interrupt Exception Handling ........................................................................................... 63
4.5 Trap Instruction Exception Handling................................................................................ 63
4.6 Stack Status after Exception Handling.............................................................................. 64
4.7 Usage Note........................................................................................................................ 65
Section 5 Interrupt Controller............................................................................ 67
5.1 Features............................................................................................................................. 67
5.2 Input/Output Pins.............................................................................................................. 68
5.3 Register Descriptions........................................................................................................ 69
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) ........................................... 69
5.3.2 Address Break Control Register (ABRKCR) ...................................................... 70
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 71
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 72
5.3.5 IRQ Enable Register (IER) .................................................................................. 73
5.3.6 IRQ Status Register (ISR).................................................................................... 73
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 73
5.4 Interrupt Sources............................................................................................................... 76
Rev. 1.00, 05/04, page x of xxxiv