Renesas H8S/2111B Hardware Manual page 32

Table 7.4 Input Pull-Up MOS States (Port 3)....................................................................... 106
Table 7.5 Input Pull-Up MOS States (Port 6)....................................................................... 116
Table 7.6 Input Pull-Up MOS States (Port A) ...................................................................... 128
Table 7.7 Input Pull-Up MOS States (Port B) ...................................................................... 131
Table 7.8 Input Pull-Up MOS States (Port C and port D) .................................................... 135
Table 7.9 Input Pull-Up MOS States (Port E and port F) ..................................................... 141
Section 8 8-Bit PWM Timer (PWM)
Table 8.1 Pin Configuration.................................................................................................. 148
Table 8.2 Internal Clock Selection........................................................................................ 150
Table 8.3 Resolution, PWM Conversion Period,
and Carrier Frequency when φ = 10 MHz ............................................................ 150
Table 8.4 Duty Cycle of Basic Pulse .................................................................................... 153
Table 8.5 Position of Pulses Added to Basic Pulses ............................................................. 154
Section 9 16-Bit Free-Running Timer (FRT)
Table 9.1 Pin Configuration.................................................................................................. 159
Table 9.2 FRT Interrupt Sources .......................................................................................... 177
Table 9.3 Switching of Internal Clock and FRC Operation.................................................. 180
Section 10 8-Bit Timer (TMR)
Table 10.1 TMR Function ...................................................................................................... 184
Table 10.2 Pin Configuration.................................................................................................. 188
Table 10.3 Clock Input to TCNT and Count Condition (1).................................................... 193
Table 10.3 Clock Input to TCNT and Count Condition (2).................................................... 194
Table 10.3 Clock Input to TCNT and Count Condition (3).................................................... 195
Table 10.4 Registers Accessible by TMR_X/TMR_Y ........................................................... 204
Table 10.5 Input Capture Signal Selection ............................................................................. 214
Table 10.6 Input Capture Signal Selection ............................................................................. 214
Table 10.7 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y,
TMR_X TMR_B, and TMR_A ............................................................................ 215
Table 10.8 Timer Output Priorities......................................................................................... 217
Table 10.9 Switching of Internal Clocks and TCNT Operation ............................................. 218
Section 11 Watchdog Timer (WDT)
Table 11.1 Pin Configuration.................................................................................................. 223
Table 11.2 WDT Interrupt Source .......................................................................................... 230
Section 12 Serial Communication Interface (SCI)
Table 12.1 Pin Configuration.................................................................................................. 236
Table 12.2 Relationships between N Setting in BRR and Bit Rate B..................................... 244
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 245
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 246
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 247
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 247
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 248
Rev. 1.00, 05/04, page xxxii of xxxiv