Figure 13.27 Iric Setting Timing And Scl Control (3) - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE =1 at transmission, or ICDRF = 1 at reception.

Figure 13.27 IRIC Setting Timing and SCL Control (3)

8
1
8
1
Clear IRIC
8
8
Clear IRIC
2
3
2
3
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00, 05/04, page 333 of 544
4
4
1
1
Clear IRIC

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