Port E And Port F Nch-Od Control Register (Penocr, Pfnocr) - Renesas H8S/2111B Hardware Manual

• PF2/TMOA
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR_A of TMR_A and the PF2DDR bit.
OS3 to OS0
PF3DDR
Pin Function
• PF1/TMIB
The pin function is switched as shown below according to the state of the PF1DDR bit.
PF1DDR
Pin Function
Note: * This pin can always be used as the TMIB input pin.
• PF0/TMIA
The pin function is switched as shown below according to the state of the PF0DDR bit.
PF0DDR
Pin Function
Note: * This pin can always be used as the TMIA input pin.
7.13.5

Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)

PENOCR and PFNOCR specify the output driver type for pins on ports E and F which are
configured as outputs on a bit-by-bit basis.
Bit Bit Name
7 PE7NOCR 0
6 PE6NOCR 0
5 PE5NOCR 0
4 PE4NOCR 0
3 PE3NOCR 0
2 PE2NOCR 0
1 PE1NOCR 0
0 PE0NOCR 0
Rev. 1.00, 05/04, page 140 of 544
0
PF2 input pin
0
PF1 input pin
0
PF0 input pin
Initial
R/W
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All 0
1
PF2 output pin
TMIB input pin*
TMIA input pin*
Description
0: CMOS (p-channel driver enabled)
1: N-channel open drain (p-channel driver disabled)
Not all 0
—
TMOA output pin
1
PF1 output pin
1
PF0 output pin