Table 22.9 I 2 C Bus Timing - Renesas H8S/2111B Hardware Manual

2
Table 22.9 I C Bus Timing
Conditions: V = 3.0 V to 3.6 V, V
CC
T = –20 to +75°C
a
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse
elimination time
SDA input bus free time
Start condition input hold time
Retransmission start condition
input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Note: * 17.5 t can be set according to the clock selected for use by the I
cyc
details, see section 13.6, Usage Notes.
= 0 V, φ = 5 MHz to maximum operating frequency,
SS
Ratings
Symbol Min. Typ.
t 12 —
SCL
t 3 —
SCLH
t 5 —
SCLL
t — —
Sr
t — —
Sf
t — —
SP
t 5 —
BUF
t 3 —
STAH
t 3 —
STAS
t 3 —
STOS
t 0.5 —
SDAS
t 0 —
SDAH
C — —
b
Test
Max. Unit Conditions Notes
— t
cyc
— t
cyc
— t
cyc
7.5* t
cyc
300 ns
1 t
cyc
— t
cyc
— t
cyc
— t
cyc
— t
cyc
— t
cyc
— ns
400 pF
2
C module. For
Rev. 1.00, 05/04, page 525 of 544
Figure
22.22