Renesas H8S/2111B Hardware Manual page 24

Section 8 8-Bit PWM Timer (PWM)
Figure 8.1 Block Diagram of PWM Timer................................................................................. 147
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 154
Figure 8.3 Example of PWM Setting.......................................................................................... 155
Figure 8.4 Example when PWM is Used as D/A Converter....................................................... 155
Section 9 16-Bit Free-Running Timer (FRT)
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ......................................................... 158
Figure 9.2 Example of Pulse Output........................................................................................... 169
Figure 9.3 Increment Timing with Internal Clock Source .......................................................... 170
Figure 9.4 Increment Timing with External Clock Source......................................................... 170
Figure 9.5 Timing of Output Compare A Output ....................................................................... 171
Figure 9.6 Clearing of FRC by Compare-Match A Signal ......................................................... 171
Figure 9.7 Input Capture Input Signal Timing (Usual Case)...................................................... 172
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ...................... 172
Figure 9.9 Buffered Input Capture Timing ................................................................................. 173
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1) ........................................................ 173
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................... 174
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 174
Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 175
Figure 9.14 OCRA Automatic Addition Timing ........................................................................ 175
Figure 9.15 Timing of Input Capture Mask Signal Setting......................................................... 176
Figure 9.16 Timing of Input Capture Mask Signal Clearing ...................................................... 176
Figure 9.17 FRC Write-Clear Conflict ....................................................................................... 177
Figure 9.18 FRC Write-Increment Conflict................................................................................ 178
Figure 9.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) ................................................. 179
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function is Used) ........................................................ 179
Section 10 8-Bit Timer (TMR)
Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 185
Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 186
Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A) .......................................... 187
Figure 10.4 Pulse Output Example ............................................................................................. 206
Figure 10.5 Count Timing for Internal Clock Input ................................................................... 207
Figure 10.6 Count Timing for External Clock Input (Both Edges) ............................................ 207
Figure 10.7 Timing of CMF Setting at Compare-Match ............................................................ 208
Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal............................. 208
Figure 10.9 Timing of Counter Clear by Compare-Match ......................................................... 208
Figure 10.10 Timing of Counter Clear by External Reset Input................................................. 209
Figure 10.11 Timing of OVF Flag Setting ................................................................................. 209
Figure 10.12 Timing of Input Capture Operation....................................................................... 213
Rev. 1.00, 05/04, page xxiv of xxxiv