21.3
Register States in Each Operating Mode
Register
High-Speed/
Abbrevia-
Medium-
tion
Reset
Speed
Initialized
TCR_B
Initialized
TCR_A
Initialized
TCSR_B
Initialized
TCSR_A
Initialized
TCORA_B
Initialized
TCORA_A
Initialized
TCORB_B
Initialized
TCORB_A
Initialized
TCNT_B
Initialized
TCNT_A
Initialized
TISR_B
Initialized
TICRR_A
Initialized
TICRF_A
Initialized
TCRAB
Initialized
TCRXY*
Initialized
SPSR*
Initialized
PGCTL*
Initialized
—
PGNOCR
Initialized
—
PENOCR
Initialized
—
PFNOCR
Initialized
—
PCNOCR
Initialized
—
PDNOCR
—
—
TWR0MW
—
—
TWR0SW
—
—
TWR1
—
—
TWR2
—
—
TWR3
—
—
TWR4
—
—
TWR5
Sub-
Watch
Sleep
Active
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Module
Software
Sub-Sleep
Stop
Standby
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 1.00, 05/04, page 497 of 544
Hardware
Standby
Module
TMR_A
Initialized
TMR_B
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
TMR_X,
TMR_Y
Initialized
SCI_1
Initialized
IIC common
Initialized
PORT
Initialized
Initialized
Initialized
Initialized
—
LPC
—
—
—
—
—
—