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5.4.1
External Interrupts ............................................................................................... 76
5.4.2
Internal Interrupts ................................................................................................ 77
5.5
Interrupt Exception Handling Vector Table...................................................................... 78
5.6
Interrupt Control Modes and Interrupt Operation ............................................................. 80
5.6.1
Interrupt Control Mode 0 ..................................................................................... 80
5.6.2
Interrupt Control Mode 1 ..................................................................................... 82
5.6.3
Interrupt Exception Handling Sequence .............................................................. 85
5.6.4
Interrupt Response Times .................................................................................... 86
5.7
Address Break................................................................................................................... 87
5.7.1
Features................................................................................................................ 87
5.7.2
Block Diagram..................................................................................................... 87
5.7.3
Operation ............................................................................................................. 88
5.7.4
Usage Notes ......................................................................................................... 88
5.8
Usage Notes ...................................................................................................................... 90
5.8.1
Conflict between Interrupt Generation and Disabling ......................................... 90
5.8.2
Instructions that Disable Interrupts ...................................................................... 91
5.8.3
Interrupts during Execution of EEPMOV Instruction.......................................... 91
5.8.4
IRQ Status Register (ISR).................................................................................... 91
Section 6 Bus Controller (BSC).........................................................................93
6.1
Register Descriptions ........................................................................................................ 93
6.1.1
Bus Control Register (BCR) ................................................................................ 93
6.1.2
Wait State Control Register (WSCR) .................................................................. 94
Section 7 I/O Ports .............................................................................................95
7.1
Port 1................................................................................................................................. 100
7.1.1
Port 1 Data Direction Register (P1DDR)............................................................. 100
7.1.2
Port 1 Data Register (P1DR)................................................................................ 100
7.1.3
Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 101
7.1.4
Pin Functions ....................................................................................................... 101
7.1.5
Port 1 Input Pull-Up MOS ................................................................................... 102
7.2
Port 2................................................................................................................................. 102
7.2.1
Port 2 Data Direction Register (P2DDR)............................................................. 102
7.2.2
Port 2 Data Register (P2DR)) .............................................................................. 103
7.2.3
Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 103
7.2.4
Pin Functions ....................................................................................................... 103
7.2.5
Port 2 Input Pull-Up MOS ................................................................................... 104
7.3
Port 3................................................................................................................................. 104
7.3.1
Port 3 Data Direction Register (P3DDR)............................................................. 104
7.3.2
Port 3 Data Register (P3DR)................................................................................ 105
7.3.3
Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 105
7.3.4
Pin Functions ....................................................................................................... 106
7.3.5
Port 3 Input Pull-Up MOS ................................................................................... 106
Rev. 1.00, 05/04, page xi of xxxiv
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