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15.2
Input/Output Pins
Table 15.1 lists the input and output pins of the LPC module.
Table 15.1 Pin Configuration
Name
LPC address/
data 3 to 0
LPC frame
LPC reset
LPC clock
Serialized interrupt request SERIRQ
LSCI general output
LSMI general output
PME general output
GATE A20
LPC clock run
LPC power-down
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
external resistor is necessary to pull the signal up to V
Abbreviation Port
LAD3 to
P33 to
LAD0
P30
LFRAME
P34
LRESET
P35
LCLK
P36
P37
LSCI
PB1
LSMI
PB0
PME
P80
GA20
P81
CLKRUN
P82
LPCPD
P83
I/O
Function
Input/
Serial (4-signal-line) transfer cycle
output
type/address/data signals,
synchronized with LCLK
1
Input*
Transfer cycle start and forced
termination signal
1
Input*
LPC interface reset signal
Input
33 MHz PCI clock signal
Input/
Serialized host interrupt request
1
output*
signal, synchronized with LCLK
(SMI, IRQ1, IRQ6, IRQ9 to
IRQ12)
1,
2
Output*
*
General output
1,
2
Output*
*
General output
1,
2
Output*
*
General output
1,
2
Output*
A20 gate control signal output
*
Input/
LCLK restart request signal in
1,
2
output*
*
case of serial host interrupt
request
1
Input*
LPC module shutdown signal
.
CC
Rev. 1.00, 05/04, page 369 of 544
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