Appendix; I/O Port States In Each Processing State; Table A.1 I/O Port States In Each Processing State - Renesas H8S/2111B Hardware Manual

A.

I/O Port States in Each Processing State

Table A.1 I/O Port States in Each Processing State
Port Name
Pin Name Reset
Port 1 T
Port 2 T
Port 3 T
Port 4 T
Port 5 T
Port 6 T
Port 7 T
Port 8 T
Port 97 T
Port 96
T
φ
EXCL
Ports 95 to 90
T
Port A T
Port B T
Ports C to G T
[Legend]
H: High
L: Low
T: High-impedance state
kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up
MOSs remain on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR used.
DDR: Data direction register

Appendix

Hardware Software
Standby Standby
Mode Mode
T kept
T kept
T kept
T kept
T kept
T kept
T T
T kept
T kept
T [DDR = 1] H
[DDR = 0] T
T kept
T kept
T kept
T kept
Watch Sleep
Mode Mode
kept kept
kept kept
kept kept
kept kept
kept kept
kept kept
T T
kept kept
kept kept
EXCL input [DDR = 1]
clock output
[DDR = 0] T
kept kept
kept kept
kept kept
kept kept
Rev. 1.00, 05/04, page 537 of 544
Sub- Subactive
sleep Mode Mode
kept I/O port
kept I/O port
kept I/O port
kept I/O port
kept I/O port
kept I/O port
T Input port
kept I/O port
kept I/O port
EXCL input EXCL input
kept I/O port
kept I/O port
kept I/O port
kept I/O port
Program
Execution
State
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Input port
I/O port
I/O port
Clock output/
EXCL input/
input port
I/O port
I/O port
I/O port
I/O port