Table 15.5 Scope Of Host Interface Pin Shutdown - Renesas H8S/2111B Hardware Manual

Table 15.5 shows the scope of the host interface pin shutdown.

Table 15.5 Scope of Host Interface Pin Shutdown

Abbreviation Port
LAD3 to LAD0 P33–P30
LFRAME
P34
LRESET
P35
LCLK P36
SERIRQ P37
LSCI PB1
LSMI
PB0
PME
P80
GA20 P81
CLKRUN
P82
LPCPD
P83
[Legend]
O: Pin that is shutdown by the shutdown function
∆:
Pin that is shutdown only when the LPC function is selected by register setting
×:
Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by STBY or RES pin input, or WDT0 overflow)
 All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
 LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
 SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
 SDWNB bit is cleared to 0.
5. LPC software shutdown
Rev. 1.00, 05/04, page 402 of 544
Scope of
Shutdown I/O
O I/O
O Input
×
Input
O Input
O I/O
∆
I/O
∆
I/O
∆
I/O
∆
I/O
O I/O
×
Input
Notes
Hi-Z
Hi-Z
LPC hardware reset function is active
Hi-Z
Hi-Z
Hi-Z, only when LSCIE = 1
Hi-Z, only when LSMIE = 1
Hi-Z, only when PMEE = 1
Hi-Z, only when FGA20E = 1
Hi-Z
Needed to clear shutdown state