Figure 13.1 Block Diagram Of I - Renesas H8S/2111B Hardware Manual

• Selectable input/output pins*
 Pins, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB, are selectable for
2
the I C bus input/output pin in each channel.
Note: * The program development tool (emulator) does not support this function.
Figure 13.1 shows a block diagram of the I
pin connections to external circuits. Since I
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 22, Electrical Characteristics.
SCL
Pin
selection
ExSCLA*
circuit
ExSCLB*
PGCTL
SDA
Pin
selection
ExSDAA*
circuit
ExSDAB*
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
ICXR:
SAR:
SARX:
PS:
PGCTL:
Note: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 278 of 544
φ
PS
Noise
canceler
Noise
canceler
2
I C bus control register
2
I C bus mode register
2
I C bus status register
2
I C bus data register
2
I C bus extended control register
Slave address register
Slave address register X
Prescaler
Port G control register

Figure 13.1 Block Diagram of I

2
C bus interface. Figure 13.2 shows an example of I/O
2
C bus interface I/O pins are different in structure from
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
2
C Bus Interface
ICXR
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address
comparator
SAR, SARX
Interrupt
generator
Interrupt
request