Usage Notes; Table 13.8 I 2 C Bus Timing (Scl And Sda Outputs) - Renesas H8S/2111B Hardware Manual

13.6

Usage Notes

1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 13.8 I C Bus Timing (SCL and SDA Outputs)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note: * 6t when IICX is 0, 12t
cyc
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
Symbol Output Timing
t 28t
SCLO
t 0.5t
SCLHO
t 0.5t
SCLLO
t 0.5t
BUFO
t 0.5t
STAHO
t 1t
STASO
t 0.5t
STOSO
t 1t
SDASO
1t
t 3t
SDAHO
when 1.
cyc
, as shown in section 22, Electrical
cyc
2
C bus interface AC timing specifications will not be met with a
to 256t
cyc cyc
SCLO
SCLO
– 1t
SCLO cyc
– 1t
SCLO cyc
SCLO
+ 2t
SCLO cyc
– 3t
SCLLO cyc
– (6t or 12t
*)
SCLL cyc cyc
cyc
Rev. 1.00, 05/04, page 337 of 544
2
C bus, neither
2
C bus output
Unit Notes
ns See figure
22.22.
ns
ns
ns
ns
ns
ns
ns
ns