Renesas HD64F2111B Manuals

Manuals and User Guides for Renesas HD64F2111B. We have 1 Renesas HD64F2111B manual available for free PDF download: Hardware Manual

Renesas HD64F2111B Hardware Manual (582 pages)

Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Brand: Renesas | Category: Computer Hardware | Size: 4 MB

Table of Contents
9
Section 1 Overview

35
- Features
  35
- Internal Block Diagram
  36
- Figure 1.1 Internal Block Diagram
  36
- Pin Description
  37
Section 2 CPU

47
Section 3 MCU Operating Modes

85
- MCU Operating Mode Selection
  85
- Table 3.1 MCU Operating Mode Selection
  85
- Register Descriptions
  86
- Operating Mode Descriptions
  90
  - Mode 2
    90
  - Mode 3
    90
- Address Map
  91
- Figure 3.1 Address Map for H8S/2111B-B
  91
- Figure 3.2 Address Map for H8S/2111B-C
  92
Section 4 Exception Handling

93
Section 5 Interrupt Controller

101
Section 6 Bus Controller (BSC)

127
- Register Descriptions
  127
  - Bus Control Register (BCR)
    127
  - Wait State Control Register (WSCR)
    128
Section 7 I/O Ports

129
- Table 7.1 Port Functions
  130
- Port 1
  134
  - Port 1 Data Direction Register (P1DDR)
    134
  - Port 1 Data Register (P1DR)
    134
  - Port 1 Pull-Up MOS Control Register (P1PCR)
    135
  - Pin Functions
    135
  - Port 1 Input Pull-Up MOS
    136
- Port 2
  136
  - Port 2 Data Direction Register (P2DDR)
    136
  - Table 7.2 Input Pull-Up MOS States (Port 1)
    136
  - Port 2 Data Register (P2DR))
    137
  - Port 2 Pull-Up MOS Control Register (P2PCR)
    137
  - Pin Functions
    137
  - Port 2 Input Pull-Up MOS
    138
- Port 3
  138
- Port 4
  141
  - Port 4 Data Direction Register (P4DDR)
    141
  - Port 4 Data Register (P4DR)
    141
  - Pin Functions
    142
- Port 5
  144
  - Port 5 Data Direction Register (P5DDR)
    144
  - Port 5 Data Register (P5DR)
    144
  - Pin Functions
    145
- Port 6
  146
  - Port 6 Data Direction Register (P6DDR)
    146
  - Port 6 Data Register (P6DR)
    147
  - Port 6 Pull-Up MOS Control Register (KMPCR)
    147
  - System Control Register 2 (SYSCR2)
    148
  - Pin Functions
    148
  - Port 6 Input Pull-Up MOS
    150
  - Table 7.5 Input Pull-Up MOS States (Port 6)
    150
- Port 7
  151
  - Port 7 Input Data Register (P7PIN)
    151
  - Pin Functions
    151
- Port 8
  152
  - Port 8 Data Direction Register (P8DDR)
    152
  - Port 8 Data Register (P8DR)
    152
  - Pin Functions
    153
- Port 9
  156
  - Port 9 Data Direction Register (P9DDR)
    156
  - Port 9 Data Register (P9DR)
    156
  - Pin Functions
    157
- Port a
  159
  - Port a Data Direction Register (PADDR)
    159
  - Port a Output Data Register (PAODR)
    159
  - Port a Input Data Register (PAPIN)
    160
  - Pin Functions
    160
  - Port a Input Pull-Up MOS
    162
  - Table 7.6 Input Pull-Up MOS States (Port A)
    162
- Port B
  163
  - Port B Data Direction Register (PBDDR)
    163
  - Port B Output Data Register (PBODR)
    163
  - Port B Input Data Register (PBPIN)
    164
  - Pin Functions
    164
  - Port B Input Pull-Up MOS
    165
  - Table 7.7 Input Pull-Up MOS States (Port B)
    165
- Ports C, D
  166
- Ports E, F
  170
- Port G
  176
  - Port G Data Direction Register
    176
  - Port G Output Data Register
    177
  - Port G Input Data Register
    177
  - Pin Functions
    178
  - Port G Nch-OD Control Register
    179
  - Pin Functions
    179
Section 8 8-Bit PWM Timer (PWM)

181
Section 9 16-Bit Free-Running Timer (FRT)

191
Section 10 8-Bit Timer (TMR)

217
Section 11 Watchdog Timer (WDT)

255
- Features
  255
- Figure 11.1 Block Diagram of WDT
  256
- Input/Output Pins
  257
- Register Descriptions
  257
  - Timer Counter (TCNT)
    257
  - Table 11.1 Pin Configuration
    257
  - Timer Control/Status Register (TCSR)
    258
- Operation
  261
  - Watchdog Timer Mode
    261
  - Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation
    262
  - Interval Timer Mode
    263
  - Figure 11.3 Interval Timer Mode Operation
    263
  - Figure 11.4 OVF Flag Set Timing
    263
  - RESO Signal Output Timing
    264
- Interrupt Sources
  264
- Figure 11.5 Output Timing of RESO Signal
  264
- Table 11.2 WDT Interrupt Source
  264
- Usage Notes
  265
Section 12 Serial Communication Interface (SCI)

269
Section 13 I C Bus Interface (IIC)

311
Section 14 Keyboard Buffer Controller

383
Section 15 Host Interface (LPC)

403
Section 16 A/D Converter

447
Section 17 RAM

463
Section 18 ROM

465
- Features
  465
- Figure 18.1 Block Diagram of Flash Memory
  466
- Mode Transitions
  467
- Figure 18.2 Flash Memory State Transitions
  467
- Table 18.1 Differences between Boot Mode and User Program Mode
  467
- Figure 18.3 Boot Mode
  468
- Figure 18.4 User Program Mode (Example)
  469
- Block Configuration
  470
- Figure 18.5 Flash Memory Block Configuration
  470
- Input/Output Pins
  471
- Register Descriptions
  471
- Operating Modes
  475
- On-Board Programming Modes
  475
- Flash Memory Programming/Erasing
  480
- Program/Erase Protection
  484
  - Hardware Protection
    484
  - Software Protection
    484
  - Error Protection
    484
- Interrupts During Flash Memory Programming/Erasing
  485
- Programmer Mode
  486
- Figure 18.11 Memory Map in Programmer Mode
  486
- Usage Notes
  487
Section 19 Clock Pulse Generator

489
Section 20 Power-Down Modes

497
- Register Descriptions
  497
- Mode Transitions and LSI States
  502
- Figure 20.1 Mode Transition Diagram
  502
- Table 20.2 LSI Internal States in each Operating Mode
  503
- Medium-Speed Mode
  504
- Figure 20.2 Medium-Speed Mode Timing
  504
- Sleep Mode
  505
- Software Standby Mode
  505
- Figure 20.3 Application Example in Software Standby Mode
  506
- Hardware Standby Mode
  507
- Figure 20.4 Hardware Standby Mode Timing
  507
- Watch Mode
  508
- Subsleep Mode
  509
- Subactive Mode
  510
- Module Stop Mode
  511
- Direct Transitions
  511
- Usage Notes
  512
  - 20.12.1 I/O Port Status
    512
  - 20.12.2 Current Consumption When Waiting for Oscillation Stabilization
    512
Section 21 List of Registers

513
- Register Addresses (Address Order)
  514
- Register Bits
  523
- Register States in each Operating Mode
  531
- Register Select Conditions
  539
Section 22 Electrical Characteristics

547
Appendix

571
Index

575

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Renesas HD64F2111B Manuals

Renesas HD64F2111B Hardware Manual (582 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 I/O Ports

Section 8 8-Bit PWM Timer (PWM)

Section 9 16-Bit Free-Running Timer (FRT)

Section 10 8-Bit Timer (TMR)

Section 11 Watchdog Timer (WDT)

Section 12 Serial Communication Interface (SCI)

Section 13 I C Bus Interface (IIC)

Section 14 Keyboard Buffer Controller

Section 15 Host Interface (LPC)

Section 16 A/D Converter

Section 17 RAM

Section 18 ROM

Section 19 Clock Pulse Generator

Section 20 Power-Down Modes

Section 21 List of Registers

Section 22 Electrical Characteristics

Appendix

Index

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