Serial Control Register (Scr) - Renesas H8S/2111B Hardware Manual

Bit Bit Name
2 MP
1 CKS1
0 CKS0
12.3.6

Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 12.7, Interrupt Sources.
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
Initial
Value R/W
0 R/W
0 R/W
0 R/W
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
Clock Select 1,0
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 12.3.9, Bit Rate
Register (BRR). n is the decimal display of the value of
n in BRR.
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 1.00, 05/04, page 239 of 544