Table 2.9 System Control Instructions; Table 2.10 Block Data Transfer Instructions - Renesas H8S/2111B Hardware Manual

Table 2.9 System Control Instructions
Instruction Size*
TRAPA —
RTE —
SLEEP —
LDC B/W
STC B/W
ANDC B
ORC B
XORC B
NOP —
Note: * Size refers to the operand size.
B: Byte
W: Word

Table 2.10 Block Data Transfer Instructions

Instruction Size
EEPMOV.B —
EEPMOV.W —
Rev. 1.00, 05/04, page 38 of 544
Function
Starts trap-instruction exception handling.
Returns from an exception-handling routine.
Causes a transition to a power-down state.
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are
valid.
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate
data.
PC + 2 → PC
Only increments the program counter.
Function
if R4L ≠ 0 then
Repeat @ER5 + → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5 + → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5,
transfers data for the number of bytes set in R4L or R4 to the
address location set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.