Renesas H8S/2111B Hardware Manual page 409

Bit single-chip microcomputer h8s family / h8s/2100 series
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Bit
Bit Name
5
IRQBSY
4
LRSTB
R/W
Initial
Value Slave Host Description
0
R
0
SERIRQ Busy
Indicates that the host interface's SERIRQ signal is
engaged in transfer processing.
0: SERIRQ transfer frame wait state
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress
[Setting condition]
Start of SERIRQ transfer frame
LPC Software Reset Bit
Resets the host interface. For the scope of initialization
by an LPC reset, see section 15.4.4, Host Interface
Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
Writing 0
LPC hardware reset
1: LPC software reset state
[Setting condition]
Writing 1 after reading LRSTB = 0
Rev. 1.00, 05/04, page 375 of 544

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