System Control Register (Syscr) - Renesas H8S/2111B Hardware Manual

3.2.2

System Control Register (SYSCR)

SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit Bit Name
7 and 6 —
5 INTM1
4 INTM0
3 XRST
2 NMIEG
Initial
Value R/W
All 0 R/W
0 R
0 R/W
1 R
0 R/W
Description
Reserved
The initial value should not be changed.
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog
timer overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 1.00, 05/04, page 53 of 544