Section 1 Overview; Features - Renesas H8S/2111B Hardware Manual

1.1

Features

• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
8-bit PWM timer (PWM)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
2
I C bus interface (IIC)
Keyboard buffer controller
Host interface (LPC)
10-bit A/D converter
Clock pulse generator
• On-chip memory
ROM
F-ZTAT Version
Note: 3-V version product
*
• General I/O ports
I/O pins: 114
Input-only pins: 8
• Supports various power-down states
• Compact package
Product
H8S/2111B

Section 1 Overview

Model
HD64F2111BVB*
HD64F2111BVC*
Package
TQFP-144
ROM RAM
64 Kbytes 2 Kbytes
64 Kbytes 3 Kbytes
Code Body Size
18.0 × 18.0 mm 0.4 mm
TFP-144
Remarks
Pin Pitch
Rev. 1.00, 05/04, page 1 of 544