Control Signal Timing; Figure 22.8 Reset Input Timing; Figure 22.9 Interrupt Input Timing - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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22.7.2

Control Signal Timing

The control signal timings are shown below.
φ
RES
φ
NMI
IRQi
(i = 7 to 0)
IRQi
Edge input
(i = 7 to 0)
IRQi
Level input
(i = 7 to 0)
t
RESS

Figure 22.8 Reset Input Timing

t
NMIS
t
IRQS
t
IRQS

Figure 22.9 Interrupt Input Timing

t
RESS
t
RESW
t
NMIH
t
NMIW
t
IRQW
t
IRQH
Rev. 1.00, 05/04, page 531 of 544

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