Figure 15.6 Serirq Timing - Renesas H8S/2111B Hardware Manual

15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a peripheral function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
15.6.
SL
or
H
LCLK
SERIRQ
IRQ1
Drive source
[Legend]
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
IRQ14 frame
S R
LCLK
SERIRQ
None
Driver
[Legend]
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Start frame
H R T
START
Host controller
IOCHCK frame
IRQ15 frame
T S R T S
IRQ15

Figure 15.6 SERIRQ Timing

IRQ0 frame IRQ1 frame
S R T S
None IRQ1
Stop frame
R T I H
STOP
None Host controller
Rev. 1.00, 05/04, page 405 of 544
IRQ2 frame
R T S R T
None
Next cycle
R T
START