22.3.1
Clock Timing
Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.
For details on external clock input (EXTAL pin and EXCL pin) timing, see section19, Clock Pulse
Generator.
Table 22.5 Clock Timing
Condition:
V
= 3.0 V to 3.6 V, V
CC
operating frequency, T
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Oscillation settling time at reset (crystal)
Oscillation settling time in software
standby (crystal)
External clock output stabilization delay
time
B = 3.0 V to 5.5 V, V
CC
= –20 to +75°C
a
Symbol
t
cyc
t
CH
t
CL
t
Cr
t
Cf
t
OSC1
t
OSC2
t
DEXT
= 0 V, φ = 4 MHz to maximum
SS
Condition
10 MHz
Min.
Max.
100
250
30
—
30
—
—
20
—
20
20
—
8
—
500
—
Rev. 1.00, 05/04, page 521 of 544
Unit
Reference
ns
Figure 22.5
ns
ns
ns
ns
ms
Figure 22.6
Figure 22.7
ms
µs