Renesas H8S/2111B Hardware Manual page 18

14.4.6 KBF Setting Timing and KCLK Control............................................................. 362
14.4.7 Receive Timing.................................................................................................... 363
14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364
14.5 Usage Notes ...................................................................................................................... 365
14.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................ 365
14.5.2 Module Stop Mode Setting .................................................................................. 366
Section 15 Host Interface (LPC) ....................................................................... 369
15.1 Features............................................................................................................................. 369
15.2 Input/Output Pins.............................................................................................................. 371
15.3 Register Descriptions........................................................................................................ 372
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ................................ 373
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ................................ 379
15.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 381
15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 382
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) .................................................. 383
15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15).................................... 383
15.3.7 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 383
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 389
15.3.9 Host Interface Select Register (HISEL)............................................................... 397
15.4 Operation .......................................................................................................................... 398
15.4.1 Host Interface Activation..................................................................................... 398
15.4.2 LPC I/O Cycles.................................................................................................... 399
15.4.3 A20 Gate.............................................................................................................. 400
15.4.4 Host Interface Shutdown Function (LPCPD) ...................................................... 403
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 407
15.4.6 Host Interface Clock Start Request (CLKRUN).................................................. 409
15.5 Interrupt Sources............................................................................................................... 410
15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 410
15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ....................... 410
15.6 Usage Notes ...................................................................................................................... 413
15.6.1 Module Stop Mode Setting .................................................................................. 413
15.6.2 Notes on Using Host Interface............................................................................. 413
Section 16 A/D Converter ................................................................................. 413
16.1 Features............................................................................................................................. 413
16.2 Input/Output Pins.............................................................................................................. 415
16.3 Register Descriptions........................................................................................................ 416
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 416
16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 417
16.3.3 A/D Control Register (ADCR) ............................................................................ 418
16.4 Operation .......................................................................................................................... 419
16.4.1 Single Mode......................................................................................................... 419
Rev. 1.00, 05/04, page xviii of xxxiv