Renesas H8S/2111B Hardware Manual page 373

Bit single-chip microcomputer h8s family / h8s/2100 series
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2
Table 13.10 I
C Bus Timing (with Maximum Influence of t
Item
t
Indication
cyc
t
0.5 t
(–t
)
SCLHO
SCLO
Sr
t
0.5 t
(–t
)
SCLLO
SCLO
Sf
t
0.5 t
–1 t
BUFO
SCLO
cyc
(–t
)
Sr
t
0.5 t
–1 t
STAHO
SCLO
cyc
(–t
)
Sf
t
1 t
(–t
)
STASO
SCLO
Sr
t
0.5 t
+ 2 t
STOSO
SCLO
cyc
(–t
)
Sr
3
t
1 t
*
–3 t
SDASO
SCLLO
cyc
(master)
(–t
)
Sr
3
t
1 t
*
SDASO
SCLL
(slave)
2
–12 t
*
cyc
(–t
)
Sr
t
3 t
SDAHO
cyc
Notes: 1. Does not meet the I
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t
6t
).
cyc
3. Calculated using the I
speed mode: 1300 ns min.).
Time Indication (at Maximum Transfer Rate) [ns]
t
Sr
Influence
(Max.)
Standard mode
–1000
High-speed mode
–300
Standard mode
–250
High-speed mode
–250
Standard mode
–1000
High-speed mode
–300
Standard mode
–250
High-speed mode
–250
Standard mode
–1000
High-speed mode
–300
Standard mode
–1000
High-speed mode
–300
Standard mode
–1000
High-speed mode
–300
Standard mode
–1000
High-speed mode
–300
Standard mode
0
High-speed mode
0
2
C bus interface specification. Remedial action such as the following
2
C bus specification values (standard mode: 4700 ns min.; high-
/t
)
Sr
Sf
2
I
C Bus
/t
Specifi-
Sf
φ =
cation
(Min.)
5 MHz
4000
4000
600
950
4700
4750
1300
1000*
4700
3800*
1300
750*
4000
4550
600
800
4700
9000
600
2200
4000
4400
600
1350
250
3100
100
400
250
1300
100
–1400*
0
600
0
600
2
C bus interface specifications are
Rev. 1.00, 05/04, page 339 of 544
φ =
φ =
8 MHz
10 MHz
4000
4000
950
950
4750
4750
1
1
1000*
1000*
1
1
3875*
3900*
1
1
825*
850*
4625
4650
875
900
9000
9000
2200
2200
4250
4200
1200
1150
3325
3400
625
700
2200
2500
1
1
–500*
–200*
375
300
375
300
1
1
1
1
SCLL

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