Timer Interrupt Enable Register (Tier) - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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9.3.6

Timer Interrupt Enable Register (TIER)

TIER enables and disables interrupt requests.
Bit
Bit Name
7
ICIAE
6
ICIBE
5
ICICE
4
ICIDE
3
OCIAE
Rev. 1.00, 05/04, page 162 of 544
Initial
Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Input Capture Interrupt A Enable
Selects whether to enable input capture interrupt A
request (ICIA) when input capture flag A (ICFA) in
TCSR is set to 1.
0: ICIA requested by ICFA is disabled
1: ICIA requested by ICFA is enabled
Input Capture Interrupt B Enable
Selects whether to enable input capture interrupt B
request (ICIB) when input capture flag B (ICFB) in
TCSR is set to 1.
0: ICIB requested by ICFB is disabled
1: ICIB requested by ICFB is enabled
Input Capture Interrupt C Enable
Selects whether to enable input capture interrupt C
request (ICIC) when input capture flag C (ICFC) in
TCSR is set to 1.
0: ICIC requested by ICFC is disabled
1: ICIC requested by ICFC is enabled
Input Capture Interrupt D Enable
Selects whether to enable input capture interrupt D
request (ICID) when input capture flag D (ICFD) in
TCSR is set to 1.
0: ICID requested by ICFD is disabled
1: ICID requested by ICFD is enabled
Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled

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