Floating-Point Unavailable Interrupt; System Call Interrupt - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
Programming Note: The ESR[PCRE,PCMP,PCRF] fields are provided to assist the

6.5.8 Floating-Point Unavailable Interrupt

A Floating-Point Unavailable interrupt occurs when no higher priority exception exists, an attempt is made to
execute a floating-point instruction which is recognized by an attached floating-point unit, and MSR[FP]=0.
When a Floating-Point Unavailable interrupt occurs, the processor suppresses the execution of the instruc-
tion causing the Floating-Point Unavailable exception, the interrupt processing registers are updated as indi-
cated below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| IVOR7[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the next instruction causing the Floating-Point Unavailable
interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.

6.5.9 System Call Interrupt

A System Call interrupt occurs when no higher priority exception exists and a system call (sc) instruction is
executed.
When a System Call interrupt occurs, the interrupt processing registers are updated as indicated below (all
registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR8[IVO] ||
0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction after the system call instruction.
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Program interrupt handler with the emulation of part of the function of
the various floating-point CR-updating instructions, when any of these
instructions cause a precise ("non-delayed") Floating-Point Enabled
exception type Program interrupt. The PowerPC Book-E floating-point
architecture defines that when such exceptions occur, the CR is to be
updated even though the rest of the instruction execution may be
suppressed. The PPC440x5 core, however, does not support such CR
updates when the instruction which is supposed to cause the update
is being suppressed due to the occurrence of a synchronous, precise
interrupt. Instead, the PPC440x5 core records in the
ESR[PCRE,PCMP,PCRF] fields information about the instruction
causing the interrupt, to assist the Program interrupt handler software
in performing the appropriate CR update manually.
Preliminary
intrupts.fm.
September 12, 2002