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l, DTC•
2.
Lotch C
3. latch A
4. latch 8
5. lotch D
6. Clock AO
7. Clock Al
8. Clock StepCtd
First Clock Cycle
1
r
1Step 1
I AO I Al
ICon- 1
I Time !Time ltrol I
1
I
I
Time
I
I
Second
I
Third
Clock Cycle
Clock Cycle
LJ
I
I
I
r--,
r l
~~-+---',
~i~,.--~--1.
~i ~~4
I
I
I
I
I
I
I
I
I
--.~~~r--1:---:-~~~r--i~~~~
I
I
I
I
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1
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1
I
•other input •ignols to the clock con initiate
0
rlock cycle.
FIGURE 48. SELECTOR
CHANN~L
A CLOCK, SIGNAL SEQUENCES
The common channel clock (I/O clock) is inhib-
ited by the diagnose word placing a bit in the IF
register. The supervisory stat allows the clock to
run for a given number of cycles.
The diagnose instruction begins from a normal
I fetch and is executed in the following fashion:
1. The quantities (B)
+
D and the immediate data
field are assembled in the storage data register
(SDR) and stored into main storage (hex address 80).
From the SDR, bit 8 of (B)
+
D is put into the I/O
mode stat. Bits 20-31 of (B)
+
D are put into ROAR.
Simultaneously immediate data bits 1-3 are put into
the sequence counter, bit 5 is put into the supervi-
sory enable storage stat, and bits 6 and 7 are put
into the progressive scan stat and the supervisory
stat respectively.
2. ROS now begins executing microinstructions
starting from the address put into its address reg-
ister.
3.
If
the supervisory stat is on, the CPU clock
is advanced synchronously with the sequence counter.
When the counter reaches zero, the progressive
scan stat is tested.
4.
If
the progressive scan stat is on, the word
following the diagnose instruction is fetched from
main storage and used as a linkage control word.
Bits 19-30 of this word are put into ROAR. At the
same time, bits 0-2 are put into the sequence
counter, bit 4 is put i~to the supervisory enable
72
(3/71)
Model SO FF.MM
storage stat, bits 5 and 6 are put into the progres-
sive scan stat and the supervisory stat, and bit 7
is put into the 1/0 mode stat. ROS begins executing
microinstructions starting at the address put into
ROAR, and step 3 is repeated. This sequence can
be extended any number of storage words, allowing
the programmer to execute any number of ROS
words in any desired order. This is the case in
progressive scan.
Selector Channel Operating Procedure Example
The selector channel operating procedure can be
summarized as follows:
1. Run all tests, printing either T(for terminate)
or fail.
2. Run all tests again and print out the results
of the error logout for each routine and load the next
routine. When this is finished, by looking at the
failing tests you can determine which test to loop on
and then
3. Loop on the selected failing routine, bypass-
ing error printouts to allow scoping.
~:
The complete progressive scan operating
procedure for the selector channel is on page
MC000-01, in Volume 1 Reference of Systems
Diagrams.
Selector Channel Test Documentation
Figure 49 shows the type of printout supplied by the
selector channel progressive scan tests. A test
failure in either or both the common channel and
selector channel is printed out. From this printout,
the following information may be obtained:
1.
Test number - Example: 1921-14.
2. Test name - Indicates what operation is being
performed; for example, IF Control Ck-Op In Test.
3. Test cycle - Defines the point in operation at
which the failure occurred; for example, Unit Select
Drop Op
In.
4. Sync point - ROS address for syncing; for
example, ROS FC5.
5. Loop number - Tells the number of times
the test was run before a failure occurred; for ex-
ample, 00.
6. Diagnose address - Address to use to loop on
the failing test for scoping. This is accomplished
by setting IC to the diagnose address and using the
repeat IAR switch; for example, 1FD8.
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