Access Control; Execute Access; Write Access; Table 5-3. Page Size And Real Address Formation - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

Table 5-3. Page Size and Real Address Formation

SIZE Page Size
0b0000 1KB
0b0001 4KB
0b0010 16KB
0b0011 64KB
0b0100 256KB
0b0101 1MB
0b0110 not supported
0b0111 16MB
0b1000 not supported
0b1001 256MB
0b1010 not supported
0b1011 not supported
0b1100 not supported
0b1101 not supported
0b1110 not supported
0b1111 not supported

5.5 Access Control

Once a matching TLB entry has been identified and the address has been translated, the access control
mechanism determines whether the program has execute, read, and/or write access to the page referenced
by the address, as described in the following sections.

5.5.1 Execute Access

The UX or SX bit of a TLB entry controls execute access to a page of storage, depending on the operating
mode (user or supervisor) of the processor.
• User mode (MSR[PR] = 1)
Instructions may be fetched and executed from a page in storage while in supervisor mode if the SX access
control bit for that page is equal to 1. If the SX access control bit is equal to 0, then instructions from that page
will not be fetched, and will not be placed into any cache as the result of a fetch request to that page while in
supervisor mode.
Furthermore, if the sequential execution model calls for the execution in supervisor mode of an instruction
from a page that is not enabled for execution in supervisor mode (that is, SX=0 when MSR[PR]=0), an
Execute Access Control exception type Instruction Storage interrupt is taken (See Interrupts and Exceptions
on page 159 for more information).

5.5.2 Write Access

The UW or SW bit of aTLB entry controls write access to a page, depending on the operating mode (user or
supervisor) of the processor.
• User mode (MSR[PR] = 1)
Store operations (including the store-class cache management instruction dcbz) are permitted to a page
in storage while in user mode if the UW access control bit for that page is equal to 1. If execution of a
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RPN bits required to be 0
none
RPN =0
20:21
RPN =0
18:21
RPN =0
16:21
RPN =0
14:21
RPN =0
12:21
not supported
RPN =0
8:21
not supported
RPN =0
4:21
not supported
not supported
not supported
not supported
not supported
not supported
Real Address
RPN || EA
0:21 22:31
RPN || EA
0:19 20:31
RPN || EA
0:17 18:31
RPN || EA
0:15 16:31
RPN || EA
0:13 14:31
RPN || EA
0:11 12:31
not supported
RPN || EA
0:7 8:31
not supported
RPN || EA
0:3 4:31
not supported
not supported
not supported
not supported
not supported
not supported
Preliminary
mmu.fm.
September 12, 2002