Figure 6-1. Virtual Address To Tlb Entry Match Process - IBM A2 User Manual

User's Manual
A2 Processor
Figure 6-1 illustrates the criteria for a virtual address to match a specific direct or indirect TLB entry, while
Table 6-1 defines the page sizes associated with each SIZE field value and the associated comparison of the
effective address to the EPN field.

Figure 6-1. Virtual Address to TLB Entry Match Process

TLBentry[ThdID(t)]
Thread t valid
TLBentry[TGS]
GS
Logical Partition ID
TLBentry[TLPID]
TLBentry[V]
TLBentry[TS]
AS
Process ID
TLBentry[TID]
EA
0:N-1
TLBentry[EPN]
0:N-1
EA
N:51
TLBentry[EPN]
N:51
TLBentry[X]
Memory Management
Page 190 of 864
=?
partition page
=?
nonguest page
=0?
=?
private page
=?
shared page
=0?
=?
>?
=0?
TLB entry matches virtual address
Legend:
{
MSR[GS] for storage accesses, or
GS
MAS5[SGS] for tlbsx[.]
MSR[IS] for instruction fetches, or
{
AS
MSR[DS] for data storage accesses, or
MAS6[SAS] for tlbsx[.]
{
PID register for storage accesses
Process ID
MAS6[SPID] for tlbsx[.]
Logical {
LPID register for storage accesses, or
Partition ID
MAS5[SLPID] for tlbsx[.]
EA effective address
N 64 – log (page size)
2
thread number (0 to 3)
t
Version 1.3
October 23, 2012