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User's Manual
A2 Processor
1.4.10.2 Clock and Power Management Interface
The CPM interface supports clock distribution and power management to reduce power consumption below
the normal operational level. External logic is necessary for the sleep mode to function.
1.5 Core Interfaces
The core includes the following interfaces:
• System interface
• Auxiliary execution unit (AXU) port
• SCOM, debug, trace, and performance monitor event ports
• Interrupt interface
• Clock and power management interface
Several of these interfaces are described briefly in the sections below.
1.5.1 System Interface
The A2 core interface has one command interface for instruction reads, data reads, and data writes, and uses
a 42-bit address bus. A full 64-byte cache line is implied for cacheable data reads and cacheable instruction
fetches. The transfer length is used to indicate 1 byte, 2 byte, 4 byte, 8 byte, 16 byte, and 32 byte for
noncacheable reads and 16 bytes for noncacheable instruction fetches. There is a 256-bit data interface for
data writes with 32 byte enables indicating which bytes should be written.
Data writes can be 1 byte, 2 byte, 4 byte, 8 byte, or 16 byte for noncacheable or cacheable writes. There is a
128-bit data reload interface for instruction reads and data reads. When the reload data is less than 16 bytes
(due to the transfer length indicating 1 byte, 2 byte, 4 byte or 8 byte), the data should be aligned within the 16
byte reload bus based on the associated command interface address. There is a back invalidate interface for
systems with an entity outside the A2 core (such as an L2 cache controller) that provide hardware cache
coherency.
A2 supports a mode that enables a 32-byte write bus to the A2 core/L2 interface. Only the AXU can produce
32-byte writes.
The command interface is a credit-based interface. The A2 core can handle up to eight load-type credits. The
actual number of load-type credits (L) that it will handle is initialized in the A2 core configuration ring. In the A2
core, there is a 12-entry load command queue that includes eight entries for data loads and four entries for
instruction fetches. An entity outside the A2 core is expected to have a near queue of L entries for load-type
operations and to give a pop indication to the A2 core as each is sent to the far queue that contains 8 to 12
entries. The specific command is indicated in the transaction type.
Examples of transaction types that expect data to be returned on the reload bus are instruction fetch, load,
and dcbt. Examples of transaction types that do not expect data to be returned on the reload bus are store,
dcbz and dcbf. The A2 core can handle up to 32 store-type credits. The actual number of credits (S) that it
will handle is initialized in the A2 core configuration ring.
Overview
Page 58 of 864
Version 1.3
October 23, 2012
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