ST STM32L4x6 Reference Manual page 1690

Revision history
Date
08-Dec-2015
1690/1693
Table 281. Document revision history (continued)
Revision
FMC
Updated BUSTURN bit description in
SRAM/NOR-Flash chip-select timing registers 1..4
(FMC_BTR1..4).
ADC
Updated VDDA in
DAC
Added
calculation with output buffer
Updated
COMP
Updated
power
OPAMP
Updated
OPAMP.
Added Note.
LCD
Updated
TSC
Added note in
acquisition
Updated
3
Added notes in CTPL and PGPSC bit description in
(continued)
Section 23.6.1: TSC control register
TIM1/TIM8
Updated
(OPM).
Updated SMS bit description in
TIM1/TIM8 slave mode control register
Updated reset value to 0xFFFF in
TIM1/TIM8 auto-reload register
TIM2/TIM3/TIM4/TIM5
Added
(OPM).
Updated SMS bitfield description in
slave mode control register
Updated CC1IF bit description in
status register
Updated reset value to 0xFFFF in
auto-reload register
TIM15/TIM16/TIM17
Updated
synchronization (TIM15
Removed bit CC2NE from
capture/compare enable register
Removed bit TIE from
DMA/interrupt enable register
DocID024597 Rev 3
Changes
Table 85: ADC
Section : Example of the sample and refresh time
on.
Table 105: Effect of low-power modes on
Table 113: Comparator behavior in the low
modes.
Table 118: Effect of low-power modes on the
Table 131: LCD behavior in low-power
Section 23.3.4: Charge transfer
sequence.
Table 137: Effect of low-power modes on
Section 26.3.21: Retriggerable one pulse mode
Section 27.3.14: Retriggerable one pulse mode
(TIMx_SMCR).
(TIMx_SR).
(TIMx_ARR).
Section 28.4.17: External trigger
only).
Section 28.5.8: TIM15
Section 28.6.3: TIM16&TIM17
(TIMx_DIER).
RM0351
Section :
pins.
DAC.
modes.
TSC.
(TSC_CR).
Section 26.4.3:
(TIMx_SMCR).
Section 26.4.12:
(TIMx_ARR).
Section 27.4.3: TIMx
Section 27.4.5: TIMx
Section 27.4.12: TIMx
(TIM15_CCER).