ST STM32L4x6 Reference Manual page 1691

RM0351
Date
08-Dec-2015
Table 281. Document revision history (continued)
Revision
Removed bit TIF from
status register
Removed bit TG from
event generation register
Updated reset value to 0xFFFF in
TIM16&TIM17 auto-reload register
TIM6/TIM7
Updated reset value to 0xFFFF in
TIM6/TIM7 auto-reload register
LPTIM
Added
RTC
Updated reference to TAMPTS bit in
Time-stamp
Updated
I2C
Updated
I2C.
Updated
USART
Replaced nCTS by CTS - nRTS by RTS - SCLK by CK.
Replaced "w" by "rc_w1" in
clear register
3
Updated
(continued)
USART.
Updated RTOF bit description in
Interrupt and status register
LPUART
Replaced nCTS by CTS - nRTS by RTS.
Updated
LPUART.
SWPMI
Updated
SWPMI.
SDMMC
Updated limit from 48 to 50 MHz in
SDMMC main
functional
control register
SDMMC clock control register (SDMMC_CLKCR)
Section 41.8.4: SDMMC command register
(SDMMC_CMD).
USB
Updated
OTG_GUSBCFG.
Updated TRDT bit description in
USB configuration register
Added
DocID024597 Rev 3
Changes
Section 28.6.4: TIM16&TIM17
(TIMx_SR).
Section 28.6.5: TIM16&TIM17
(TIMx_EGR).
Section 30.5: LPTIM low power
function.
Table 172: Effect of low-power modes on
Table 188: Effect of low-power modes on the
Table 175: STM32L4x6 I2C
Section 36.8.9: Interrupt flag
(USARTx_ICR).
Table 197: Effect of low-power modes on the
(USARTx_ISR).
Table 202: Effect of low-power modes on the
Table 215: Effect of low-power modes on
features, Section 41.3: SDMMC
description, Section 41.8.1: SDMMC power
(SDMMC_POWER),
Section : Choosing the value of TRDT in
(OTG_GUSBCFG).
Table 261: TRDT values.
Revision history
Section 28.6.10:
(TIMx_ARR).
Section 29.4.8:
(TIMx_ARR).
modes.
Section 34.3.13:
RTC.
implementation.
Section 36.8.8:
Section 41.1:
Section 41.8.2:
and in
Section 43.15.4: OTG
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