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Booting
The ROM Code uses the row pointed by the MBOOT configuration value .The device list is filled in with
the 1st to 4th devices.
Table 21-8
is the decoding table for MBOOT configuration pins. The following shortcuts are used in the
table:
NAND / NANDI2C
XIP / XIP w/ WAIT
UART
Ethernet
SPI
PCIE_32 / PCIE_64
The values mentioned in the last row and corresponding MBOOT[4:0]= x1111 when used on an
EMULATOR device correspond to the HW assisted external booting feature offered. In that case, the
ROM Code is fully bypassed and starts up from reset vector 0x0 routed to the GPMC. This feature is
fully driven by HW without any SW involvement. In this configuration the MBOOT[15] signal selects
whether the WAIT signal must be monitored on the GPMC interface. The external boot feature is not
available.
However in the case of GP device, a "Fast XIP boot mechanism" (as described in
provided where minimal execution is performed from ROM Code for configuring the GPMC interface
and then directly jump to the code contained in the connected NOR flash device.
The NOR device must fulfill the following requirements for EMU external boot mode and GP fast XIP
mode:
•
Addr/Data muxed device or a non-muxed device in connected in MUX0 configuration
•
Bus width selected by MBOOT[12]
•
CS0 chip select
•
Device wait signal connected to the WAIT0 GPMC signal (if used)
•
The wait monitoring enable/disable is based on the value of MBOOT[15]
1998
ROM Code Memory and Peripheral Booting
Preliminary
NAND flash memory / read flash geometry from I2C EEPROM
NOR or other XIP device with or without wait monitoring
UART interface (UART port 0)
Ethernet GMII0 interface (EMAC port 0)
SPI EEPROM (SPI 0, CS0)
PCI Express interface with 32 bit / 64 bit addressing
© 2011, Texas Instruments Incorporated
www.ti.com
Section
21.6) is
SPRUGX9 – 15 April 2011
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