Display Data Read; Read To Write And Write To Read; Programmable Fields In Bypass Mode - Texas Instruments OMAP36 Series Technical Reference Manual

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L4_CLK
RFBI_A0(D/C)
RFBI_CSi
(with i = 0, 1)
RFBI_RD
RFBI_DA[15:0]
L4_CLK
RFBI_A0(D/C)
RFBI_CSi
(with i = 0, 1)
RFBI_RD
RFBI_WR
RFBI_DA[15:0]
• Timing diagrams in bypass mode
Figure 7-17 through
bypass mode for both passive matrix and active matrix panels. The display controller directly drives
these signals, which are related to the programmable fields described in
Name Register
PPL DSS.DISPC_SIZE_LCD[10:0] PPL bit field value + 1
LPP DSS.DISPC_SIZE_LCD[26:16] LPP bit field value + 1
HBP DSS.DISPC_TIMING_H[31:20] HBP bit field value + 1
HFP DSS.DISPC_TIMING_H[19:8] HFP bit field value + 1
HSW DSS.DISPC_TIMING_H[7:0] HSW bit field value + 1
VBP DSS.DISPC_TIMING_V[31:20] VBP bit field value
SWPU177N – December 2009 – Revised November 2010
Public Version
Figure 7-15. Display Data Read
AccessTime
RECycleTime
CSOffTime
CSOnTime
REOffTime
REOnTime
DATA0
Figure 7-16. Read to Write and Write to Read
RECycleTime
CSOffTime
CSOnTime
READ0
Figure 7-32 show timing diagrams of synchronization signals and pixel clock in
Table 7-7. Programmable Fields in Bypass Mode
Copyright © 2009–2010, Texas Instruments Incorporated
CSOnTime
REOffTime
DATA1
CSPulseWidth
WECycleTime
CSOffTime
CSOnTime
WRITE0
Description
Pixels per line (PPL)
Lines per panel
Horizontal back porch
Horizontal front porch
Horizontal synchronization pulse width
Vertical back porch
Display Subsystem Environment
dss-013
CSPulseWidth
CSOffTime
CSOnTime
READ1
dss-014
Table 7-7.
Display Subsystem
1579