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2.7.3 Caches and Write Buffer
The ARM926EJ-S processor includes:
•
An Instruction cache (Icache)
•
A Data cache (Dcache)
•
A write buffer
The size of the data cache is 16 KB, instruction cache is 16 KB, and write buffer is 17 bytes.
The caches have the following features:
•
Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)
•
Four-way set associative, with a cache line length of eight words per line (32 bytes per line), and two
dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
Perform critical-word first cache refilling
•
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown and controlling cache pollution.
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the
TAGRAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations to provide efficient invalidation of the following:
– The entire Dcache or Icache
– Regions of the Dcache or Icache
– The entire Dcache
– Regions of virtual memory
•
They also provide operations for efficient cleaning and invalidation of the following:
– The entire Dcache
– Regions of the Dcache
– Regions of virtual memory
The write buffer is used for all writes to a non-cachable bufferable region, write-through region, and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines.
The main write buffer has a 16-word data buffer and a four-address buffer.
The Dcache write-back has eight data word entries and a single address entry.
The MCR drain write buffer enables both write buffers to be drained under software control.
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be
put into a low power state until an interrupt occurs.
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from
SPRUGX5A – May 2011
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