Timing Waveform For Basic Sdram Write Operation - Texas Instruments AM1808 Technical Reference Manual

Sitara arm microprocessor

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Architecture

19.2.4.10 SDRAM Write Operations

When the EMIFA receives a write request to SDRAM from one of the requesters listed in

performs one or more write-access cycles. A write-access cycle begins with the issuing of the ACTV

command to select the desired bank and row of the SDRAM device. After the row has been opened, the

EMIFA proceeds to issue a WRT command while specifying the desired bank and column address.

EMA_A[10] is held low during the WRT command to avoid auto-precharging. The WRT command signals

the SDRAM device to start writing a burst of data to the specified address while the EMIFA issues NOP

commands. The associated write data will be placed on the data bus in the cycle concurrent with the WRT

command and with subsequent burst continuation NOP commands.

shows the signal waveforms for a basic SDRAM write operation in which a burst of data is

read from a single page. When the EMIFA SDRAM interface is configured to 16-bit by setting the NM bit

of the SDRAM configuration register (SDCR) to 1, a burst size of eight is used.

size of eight.

Figure 19-6. Timing Waveform for Basic SDRAM Write Operation

The EMIFA will truncate a series of bursting data if the remaining addresses of the burst are not part of

the write request. The EMIFA can truncate the burst in three ways:

By issuing another WRT to the same page

By issuing a PRE command in order to prepare for accessing a different page of the same bank

By issuing a BT command in order to prepare for accessing a page in a different bank

Several other pins are also active during a write access. The EMA_WE_DQM[1:0] pins are driven to select

which bytes of the data word will be written to the SDRAM device. They are also used to mask out entire

undesired data words during a burst access. The state of the other EMIFA pins during each command can

The EMIFA schedules its commands based on the timing information that is provided to it in the SDRAM

timing register (SDTIMR). The values for the timing parameters in this register should be chosen to satisfy

the timing requirements listed in the SDRAM datasheet. The EMIFA uses this timing information to avoid

violating any timing constraints related to issuing commands. This is commonly accomplished by inserting

NOP commands during various cycles of an access. Refer to the register description of SDTIMR in

Section 19.4.6

for more details on the various timing parameters.

External Memory Interface A (EMIFA)

SPRUH82C – April 2013 – Revised September 2016

shows a burst

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