Interface Settings - Texas Instruments TPS65941213-Q1 User Manual

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Register Name Field Name
FREQ_SEL BUCK1_FREQ_SEL
BUCK2_FREQ_SEL
BUCK3_FREQ_SEL
BUCK4_FREQ_SEL
BUCK5_FREQ_SEL
FSM_STEP_SIZE PFSM_DELAY_STEP
LDO_RV_TIMEOUT_ LDO1_RV_TIMEOUT
REG_1
LDO2_RV_TIMEOUT
LDO_RV_TIMEOUT_ LDO3_RV_TIMEOUT
REG_2
LDO4_RV_TIMEOUT
USER_SPARE_REGS USER_SPARE_1
USER_SPARE_2
USER_SPARE_3
USER_SPARE_4
ESM_MCU_MODE_ ESM_MCU_EN
CFG
ESM_SOC_MODE_ ESM_SOC_EN
CFG
CUSTOMER_NVM_ID_ CUSTOMER_NVM_ID
REG
RTC_CTRL_2 XTAL_EN
LP_STANDBY_SEL
FAST_BIST
STARTUP_DEST
XTAL_SEL
PFSM_DELAY_REG_1 PFSM_DELAY1
PFSM_DELAY_REG_2 PFSM_DELAY2
PFSM_DELAY_REG_3 PFSM_DELAY3
PFSM_DELAY_REG_4 PFSM_DELAY4
GENERAL_REG_0 FAST_BOOT_BIST
GENERAL_REG_1 REG_CRC_EN

5.11 Interface Settings

These settings detail the default interface, interface configurations, and device addresses. These settings cannot
be changed after device startup.
Register Name Field Name
SERIAL_IF_CONFIG I2C_SPI_SEL
I2C1_SPI_CRC_EN
I2C2_CRC_EN
I2C1_ID_REG I2C1_ID
I2C2_ID_REG I2C2_ID
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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Table 5-10. Miscellaneous NVM Settings (continued)
TPS65941213-Q1
Value Description
0x0 2.2 MHz
0x0 2.2 MHz
0x0 2.2 MHz
0x0 2.2 MHz
0x0 2.2 MHz
0xb 0xb
0xf 16ms
0xf 16ms
0xf 16ms
0xf 16ms
0x0 0x0
0x0 0x0
0x0 0x0
0x0 0x0
0x0 ESM_MCU disabled.
0x0 ESM_SoC disabled.
0x0 0x0
0x0 Crystal oscillator is disabled
0x0 LDOINT is enabled in standby
state.
0x0 Logic and analog BIST is run
at BOOT BIST.
0x3 ACTIVE
0x0 6 pF
0x58 0x58
0x9d 0x9d
0x0 0x0
0x0 0x0
0x0 LBIST is run during boot BIST 0x0
0x1 Register CRC enabled
Table 5-11. Interface NVM Settings
TPS65941213-Q1
Value Description
0x0 I2C
0x0 CRC disabled
0x0 CRC disabled
0x48 0x48
0x12 0x12
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TPS65941111-Q1
Value
0x0
0x0
0x0
0x0
0x0
0xb
0xf
0xf
0xf
0xf
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x3
0x0
0x0
0x1d
0x0
0x0
0x1
TPS65941111-Q1
Value
0x0
0x0
0x0
0x4c
0x13
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Static NVM Settings
Description
2.2 MHz
2.2 MHz
2.2 MHz
2.2 MHz
2.2 MHz
0xb
16ms
16ms
16ms
16ms
0x0
0x0
0x0
0x0
ESM_MCU disabled.
ESM_SoC disabled.
0x0
Crystal oscillator is disabled
Low power standby state
is used as standby state
(LDOINT is disabled).
Logic and analog BIST is run
at BOOT BIST.
ACTIVE
6 pF
0x0
0x1d
0x0
0x0
LBIST is run during boot BIST
Register CRC enabled
Description
I2C
CRC disabled
CRC disabled
0x4C
0x13
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Jacinto™ 7 J721E, PDN-0C