Debugging Mac Interface - Texas Instruments DP83867 Troubleshooting Manual

Troubleshooting the Application

2.7 Debugging MAC Interface

2.7.1 RGMII Debug
Reference the waveforms in this section verify the expected MAC data and clock signals for RGMII in shift
and align modes. To capture data and clock signals, measure close to the receiver end. Note the following
requirements for selecting the correct delay mode:
If MAC's Configuration is
RGMII Align Mode on TX side
RGMII Align Mode on RX side
RGMII Shift Mode on TX side
RGMII Shift Mode on RX side
In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register (RGMIIDCTL),
address 0x0086.
RX_D[3:0] Data Aligned with RX_CLK
For the PHY set in RX align mode in 10/100Mbps, probe the clock and data signals on the MAC end and
compare to the reference waveforms shown below:
Verify the frequency of the clock (C2) as 2.5MHz, and the data (C1) being sampled at the rising edge of the
clock.
14 DP83867 Troubleshooting Guide
Table 2-7. Selecting the Correct RGMII Delay Mode
Note
Figure 2-11. 10 Mbps Data Aligned with RX_CLK
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Required PHY Configuration
RGMII Shift Mode on TX side
RGMII Shift Mode on RX side
RGMII Align Mode on TX side
RGMII Align Mode on RX side
SNLA246C – OCTOBER 2015 – REVISED APRIL 2024
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